The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a method for forming a capacitor.
Generally, a capacitor includes conductive materials capable of supplying current, which are separated from each other with a given space. In addition, a dielectric material with a specific dielectric constant is placed between the conductive materials. Capacitance of a capacitor is proportional to an effective area of the capacitor and a dielectric constant of a dielectric material, and is inversely proportional to a distance between the conductive materials.
With increasing integration in semiconductor memory devices, there have been developed technologies that increase capacitance of the capacitor in order to compensate for reducing the two-dimensional size of storage nodes. First, for example, there is a technology that increases vertical area of a capacitor. According to the technology, an oxide film formed in a capacitor with a stacking method can be made thicker, and in a trench method, an effective area of the capacitor can be increased by more deeply etching a silicon substrate.
Second, there is a technology that reduces a thickness of a dielectric film used in a capacitor or deposits dielectric film with a high dielectric constant. For example, elements with heavy atomic weight such as Hf, Zr, Ta or St are used solely or in combinations thereof to form the dielectric film with high dielectric constant (high-k) materials, or the atomic layer deposition (ALD) method is used to form the dielectric film with thickness of a few angstroms.
Third, there is a technology that changes a structure of a capacitor to increase its effective area. The effective area of the capacitor can be increased by growing metastable-polysilicon (MSP) on a surface of the capacitor to form an uneven surface, after the capacitor is patterned, or by performing selective chemical etching on an oxide film where the capacitor pattern is formed.
Among the above described technologies of forming the capacitor, when thin high-k materials are deposited to form the dielectric film, a leakage current may be generated through the dielectric film. This leakage current leads to the loss of charge stored in a storage node, which may result in the loss of stored information.
Meanwhile, for electrically connecting between a wiring layer (i.e., a bit line) under the storage node, and a metal wiring layer formed over the storage node in a DRAM memory device, a deep contact hole is formed and filled with a conductive material to form a via contact.
In that case, as aspect ratios of the storage node and the via contact hole increase, it the process difficulty increases, and the defective rate also increases in the course of the process.
In addition, when the etching process is performed in order to form a contact hole having a large aspect ratio, there can be a difference between the upper diameter of the contact hole and the lower diameter thereof. If the difference between the upper and lower diameters is large, the via contact hole may not be completely etched down to the bottom, thereby causing a so-called “hole-not-open” phenomenon. Also, a process difficulty increases for filling the storage node and the contact hole with the conductive materials.